From: Phil Budne Date: Mon, 24 Jul 2000 14:43:42 -0400 (EDT) From: budd@csa.bu.edu (Phil Budne) Subject: Re: Clarification desired re: instructions on KA10 Date: 11 Sep 1998 00:00:00 GMT Message-ID: <6tbubq$kef$1@news1.bu.edu> References: Organization: Computer Science Department, Boston University, Boston, MA, USA Followup-To: alt.sys.pdp10 Newsgroups: alt.sys.pdp10 In article , Mark Crispin wrote: >Unfortunately, I do not have any PDP-6 prints See http://www.ai.mit.edu/people/tk/pdp6/pdp6.html >I thought that I had a comparison chart that covered the PDP-6 Here is information from Appendix E of HARDWARE REFERENCE MANUAL DEC-10-XSRNA-A-D (Feb 1975) which covers the PDP-6 the KA10 and the KI10. I'm leaving out the KI and any area where the '6 and the KA are the same, and summarizing some text; Address Break PDP-6 No. KA10 Switch and flag Address stop PDP-6 switches compared with virtual addresses (unreloacted) KA10 switches compared with physical addresses (relocated) Byte pointer incrementing PDP-6 Address overflow carries into index field, and EA calc from the pointer uses the new index register KA10 Address overflow carries, but ILDB or IDPB use original index register, unless an interrupt occurs between the two parts of the the instruction, in which case the updated index register is used. Carry flags PDP-6 Subtractiuon done in 3 steps: complement minuend, add, complement sum. The resulting effect on the Carry flags is the opposite of that listed of SUB, SOJ and SOS KA10 Subtraction done directly Clock PDP-6 Progrm must diable Clock interrupts when opertator is using single instruction mode KA10 The flags is disabled when single isntruction mode is on Console programming PDP-6 DATAI APR, KA10 DATAI APR, and DATAO PI, to load MI First Part Done PDP-6 Set only by interrupt between parts of an IDPB or ILDB, and cleared only when the PC word is saved by an interrupt instruction or an instruction executed by a UUO. (Flag is often reffered to as Byte Increment Supression) KA10 Set same as PDP-6, but cleared whenever PC word is saved. Floating Overflow PDP-6 No. KA10 Yes - in PC and processor conditions. FP Instructions PDP-6 FSC plus four standard operations, with and without rounding, in basic, Long, Memory and Both modes. KA10 PDP-6 complement, except Immediate replaces Long with routing, plus UFA and DFN to facilitate double precision. FP Immediate mode PDP-6 No. KA10 Yes - operand E,0, but only with rounding (FADRI, FSBRI, FMPRI, FDVRI) FP Long mode FADL, FSBL, FMPL PDP-6 In low order word, fraction begins in bit 1 (no exponent) and sign is not forced to 0. KA10 Low order word has fraction and expoenet in standard software format. FP Long mode With rounding PDP-6 Stores meaningless low order word or remainder KA10 Replaced by immediate mode. FP Long mode: FDVL PDP-6 Remainder is incorrect and lacks exponent KA10 Correct remainder stored in std. FP format, but not normalized FP Normalization PDP-6 In add subtract and multiply if high order word of double length result is (positive) zero, no normalization takes place. In FSC h/w does not normalize result. KA10 Result always normalized (except UFA and DFN) FP Rounding PDP-6 If low order part is exactly 1/2 LSB in a negative number, rounding is toward zero KA10 A low order part of exactly 1/2 LSB is rounded away from zero Floating Underflow PDP-6 No. KA10 Yes - in PC word and processor conditions HALT PDP-6 Cannot be performed in user mode. KA10 Can be performed in user mode only if User In-out set. IDIV PDP-6 Overflow if dividend -2^35 KA10 Dividend -2^35 OK except No Divide if divisor +/-1. Interrupt locations PDP-6 Executive (physical) locations 42-57 KA10 Executive (physical) locations 42-57 or 142-157 if offset Interrupt instructions PDP-6 Must use JSR to enter interrupt routine. KA10 Can use JSR, JSP, JSA, PUSHJ or JRST to enter interrupt routine Interruipt points PDP-6 Before instruction fetch and each address word fetch KA10 After each instruction fetch and each address word fetch CONI PI, PDP-6 bits 21-27 not used KA10 bits 21-27 show interrupts in progress JEN PDP-6 Cannot be performed in user mode. KA10 Can be performed in user mode if User In-out set. JFCL bit 12 (JFCL 1,) PDP-6 PC Chhange KA10 Floating Overflow JFFO PDP-6 No. KA10 Yes. JRSTF (JRST 2,) PDP-6 When used with indexing (no indirect) restores flags correctly only if previous instruction leaves left half of AR clear. KA10 No problem. Memory management PDP-6 One each, protection and relocation registers. KA10 Two each, protection and relocation registers. Memory Protection Interrupt PDP-6 After an illegal user reference, the interrupt occurs before the next instruction fetch KA10 After an illegal user reference, the processor executes a zero instruction (UUO), which is trapped in executive location 40. The interrupt occurs after the instruction in executive location 41 is fetched. Memory references PDP-6 memory references are made in SETZ, SETO, SETA annd SETCA KA10 unnecessary references of the PDP-6 are not made. No Divide PDP-6 No. KA10 Yes - In PC word. Overflow PDP-6 Overflow (arithmetic) and Pushdown Overflow flags, which cause interrupts. Overflow conditions set flags in all circumstances. KA10 PDP-6 plus Floating Overflow, Floating Underfloa and No Divide flags. PC Change PDP-6 Yes. KA10 No. PC Word PDP-6 0 Overflow 3 PC Change KA10 0 Overflow 3 Floating Overflow 11 Floating Underflow 12 No Divide Processior conditions: CONO APR, PDP-6 27 Disable PC Change Interrupt 28 Enable PC Change Interrupt 29 Clear PC Change KA10 21 Clear Address Break 27 Clear Floating Overflow Interrupt 28 Enable Floating Overflow Interrupt 29 Clear Floating Overflow Processior conditions: CONI APR, PDP-6 28 PC Change Interrupt Enabled 29 PC Change KA10 28 Floating Overflow Interrupt Enabled 29 Floating Overflow 30 Trap Offset Parity Error PDP-6 No. KA10 Read by CONI PI, POP AC,AC PDP-6 AC receives decremented pointer KA10 AC receives word taken from stack and pointer is lost Power Failure PDP-6 No. KA10 Read by CONI PI, Program management PDP-6 User can necver give HALT or JEN can use IO only if User In-out set Illegal instruction executes as UUO KA10 IO, HALT and JEN illegal unless User In-out set, in which case all are legal. Illgeal instruction executes as MUUO. Read-in PDP-6 No hardware read in; key allows access to readin area (first 16 core locations) for bootstrap. KA10 Yes. Ends by executing last word in the block as instruction Trap Offset PDP-6 No. KA10 Turning off MA TRP OFFSET switch sets flag (a proc cond) Unssigned codes PDP-6 100-131, 243, 247, 257. On most machines these execute like UUOs, but use executive locations 60-61; on some machines the execute as no-ops (there is no standard) [!!!] KA10 247 and 257 are not regarded as unassigned and execute as noops unless implemented by special hardware. Unimplemented operations PDP-6 If FP and byte instructions are not implemented in h/w codes 132-177 act like unassigned codes. User In-out PDP-6 Allows IO instructions to be performed in user mode. KA10 Allows IO instructions, HALT and JEN to be performed in user mode. UUO PDP-6 All UUOs 000-077 use executive locations 40-41 KA10 LUUOs 001-037 use user locations 40-41 in user mode executive locations 40-41 in executive mode. MUUOs and 040-077 use executive locations 40-41 (Trap offset changes executive locations 40-41 to 140-141)