From nobody Wed Sep 4 09:12:34 2002 Sender: eric@ruckus.brouhaha.com From: Eric Smith Newsgroups: comp.arch,alt.folklore.computers Subject: Re: What was the size of Microcode in various machines References: <3D6EA8D1.1CE008B7@cisco.com> <3D743E47.4A05925@jps.net> <85wuq3r4y6.fsf@junk.nocrew.org> Organization: Eric Conspiracy Secret Labs X-Eric-Conspiracy: There is no conspiracy. Date: 03 Sep 2002 16:19:21 -0700 Message-ID: Lines: 30 User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii NNTP-Posting-Host: 209.66.107.17 X-Trace: 3 Sep 2002 16:43:50 -0700, 209.66.107.17 Path: junk.nocrew.org!uni-berlin.de!fu-berlin.de!enews.sgi.com!news.spies.com!209.66.107.17 Xref: junk.nocrew.org comp.arch:11051 alt.folklore.computers:19345 Lars Brinkhoff writes: > I'm not sure, but these may be the microcode widths and sizes of some > PDP-10 processors: > > DEC KL10 model A 96 bits x 1280 words > DEC KL10 model B 96 bits x 2K words Really only about 80 bits per microword, as not all of the bits are actually implemented in the hardware. The microassembler produces 96-bit words, but the extra bits get dropped on the floor when loaded into the hardware. The KL10 "model A" described in the System Reference Manual refers to the KL10-PA Arithmetic Processor, and the "model B" refers to the KL10-PV. Note that these are used in various models with a single letter suffix, so a KL10-B is actually a "model A" (unless field upgraded). There was reportedly a cancelled KL10 model that would have expanded the control store to 4K words. This would have been nice as the KL10-PV microcode was at the size limit and features were getting removed to make room for bug fixes. > DEC KS10 96 bits x 2K words The microsequencer has 12-bit addresses, and the branch field in the microword is 12 bits wide, so in principle the KS10 microstore could be expanded to 4K words. However, DEC had a hard time squeezing even the 2K words into the space available using the SRAM chips they could get in 1977. And they had a lot of problems with those SRAM chips, leading to a patented technique where a control store parity error would cause the front-end processor to initiate an on-the-fly microcode reload.