From "The MAXC Microprocessor" by Butler Lampson, Ed Fiala, Ed
McCreight, and Chuck Thacker, July 26 1972:

  [Chapter 1, page 3]
  Data transfers to  and from this bus and all  other functions in the
  machine  are under  control of  a 72-bit  microinstruction  word.  A
  machine  may  be  configured  with  either 1024  or  2048  words  of
  instruction memory.
  [...]
  The machine is synchronous, with a cycle time of 150 ns.

  [Chapter 1, page 4]
  This  memory is  a 512K  (expandable to  1024K) x  40 bit  (+8 error
  correction and detection bits)  dynamic MOS system.  Access time and
  cycle time are 800 ns.
  [...]
  It is  connected to a controlling minicomputer  (Data General Nova),
  which has the task of  monitoring the system for errors and abnormal
  conditions.  This  interface is used for debugging  microcode in the
  processor  under control  of a  debugger in  the Nova.   The control
  memory of the  microprocessor is loaded via this  interface at start
  up, during debugging, and when errors occur during normal operation.

  [Chapter 4, page 20]
  The processory physically contains  three 1024 word memories with 18
  bits/word (plus  parity).  These are  logically arranged as  two 512
  word x  36-bit memories caleld  the scratchpad (S) and  the dispatch
  memory (D), and an 18-bit memory called the MAP.

  [Chapter 4, page 21]
  4.3 Map Memory (MAP, MP)

  Since this memory has 1024  18-bit words, it needs a 10-bit address.
  The Y register is used for the bottom 9 bits.  The top bit, which in
  the intended  use selects the  user map 91)  or monitor map  (0), is
  taken from the current user mode (CUM) bit of F.

  [Chapter 5, page 23]
  The  memory interface used  by normal  (non-interrupt) microprograms
  consists of a 40-bit data  register (MDR), a 21-bit address register
  (MAR), and  circuitry to implement the  request-response protocol of
  the main memory system.

  [Chapter 6, page 27]
  The maintenance  interface has two independent  function.  The first
  is to  facilitate 16-bit data transfer  between the NOVA  and any of
  256   external  devices,   several  of   which  are   used   by  the
  microprocessory; the  second is to process interrupts  from the MAXC
  system used for interprocessor communication and error reporting.