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Date: Fri, 6 Sep 2002 10:31:20 -0700
From: Dave Conroy <dgc@spies.com>
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Subject: Re: fpga pdp-10 status report
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The PA is 22 bits (the memory is actually 8Mx18, double-pumped)
There is no cache
The TB holds 1024 entries (even though ITS uses 1K pages, the TB works
in 512W pages)
The microcode is highly vertical, 24-bits wide.
By traditional standards the control store is huge (32K, implemented
with 3 32Kx8 SRAMS). About 6K locations actually have stuff
in them right now (although I don't do double float yet). The design
encourages the use of control words. The main dispatch is
a 512-way jump into 32-word slots in the top 16K, and there is little
reason to share code (for example, all of the I/O instructions,
except for ones of the form 70x, have exactly the same implementation, but
the code is just replicated into *every* slot).
dgc