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INFO-DIR-SECTION Programming
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* gcc: (gcc).                  The GNU Compiler Collection.
END-INFO-DIR-ENTRY
   This file documents the use and the internals of the GNU compiler.


   Published by the Free Software Foundation
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   A GNU Manual

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   You have freedom to copy and modify this GNU Manual, like GNU
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File: gcc.info,  Node: MIPS Options,  Next: i386 and x86-64 Options,  Prev: RT Options,  Up: Submodel Options

MIPS Options
------------

   These `-m' options are defined for the MIPS family of computers:

`-march=CPU-TYPE'
     Assume the defaults for the machine type CPU-TYPE when generating
     instructions.  The choices for CPU-TYPE are  `r2000', `r3000',
     `r3900', `r4000', `r4100', `r4300', `r4400', `r4600', `r4650',
     `r5000', `r6000', `r8000', and `orion'.  Additionally, the
     `r2000', `r3000', `r4000', `r5000', and `r6000' can be abbreviated
     as `r2k' (or `r2K'), `r3k', etc.

`-mtune=CPU-TYPE'
     Assume the defaults for the machine type CPU-TYPE when scheduling
     instructions.  The choices for CPU-TYPE are `r2000', `r3000',
     `r3900', `r4000', `r4100', `r4300', `r4400', `r4600', `r4650',
     `r5000', `r6000', `r8000', and `orion'.  Additionally, the
     `r2000', `r3000', `r4000', `r5000', and `r6000' can be abbreviated
     as `r2k' (or `r2K'), `r3k', etc.  While picking a specific
     CPU-TYPE will schedule things appropriately for that particular
     chip, the compiler will not generate any code that does not meet
     level 1 of the MIPS ISA (instruction set architecture) without a
     `-mipsX' or `-mabi' switch being used.

`-mcpu=CPU-TYPE'
     This is identical to specifying both `-march' and `-mtune'.

`-mips1'
     Issue instructions from level 1 of the MIPS ISA.  This is the
     default.  `r3000' is the default CPU-TYPE at this ISA level.

`-mips2'
     Issue instructions from level 2 of the MIPS ISA (branch likely,
     square root instructions).  `r6000' is the default CPU-TYPE at this
     ISA level.

`-mips3'
     Issue instructions from level 3 of the MIPS ISA (64-bit
     instructions).  `r4000' is the default CPU-TYPE at this ISA level.

`-mips4'
     Issue instructions from level 4 of the MIPS ISA (conditional move,
     prefetch, enhanced FPU instructions).  `r8000' is the default
     CPU-TYPE at this ISA level.

`-mfp32'
     Assume that 32 32-bit floating point registers are available.
     This is the default.

`-mfp64'
     Assume that 32 64-bit floating point registers are available.
     This is the default when the `-mips3' option is used.

`-mfused-madd'
`-mno-fused-madd'
     Generate code that uses (does not use) the floating point multiply
     and accumulate instructions, when they are available.  These
     instructions are generated by default if they are available, but
     this may be undesirable if the extra precision causes problems or
     on certain chips in the mode where denormals are rounded to zero
     where denormals generated by multiply and accumulate instructions
     cause exceptions anyway.

`-mgp32'
     Assume that 32 32-bit general purpose registers are available.
     This is the default.

`-mgp64'
     Assume that 32 64-bit general purpose registers are available.
     This is the default when the `-mips3' option is used.

`-mint64'
     Force int and long types to be 64 bits wide.  See `-mlong32' for an
     explanation of the default, and the width of pointers.

`-mlong64'
     Force long types to be 64 bits wide.  See `-mlong32' for an
     explanation of the default, and the width of pointers.

`-mlong32'
     Force long, int, and pointer types to be 32 bits wide.

     If none of `-mlong32', `-mlong64', or `-mint64' are set, the size
     of ints, longs, and pointers depends on the ABI and ISA chosen.
     For `-mabi=32', and `-mabi=n32', ints and longs are 32 bits wide.
     For `-mabi=64', ints are 32 bits, and longs are 64 bits wide.  For
     `-mabi=eabi' and either `-mips1' or `-mips2', ints and longs are
     32 bits wide.  For `-mabi=eabi' and higher ISAs, ints are 32 bits,
     and longs are 64 bits wide.  The width of pointer types is the
     smaller of the width of longs or the width of general purpose
     registers (which in turn depends on the ISA).

`-mabi=32'
`-mabi=o64'
`-mabi=n32'
`-mabi=64'
`-mabi=eabi'
     Generate code for the indicated ABI.  The default instruction
     level is `-mips1' for `32', `-mips3' for `n32', and `-mips4'
     otherwise.  Conversely, with `-mips1' or `-mips2', the default ABI
     is `32'; otherwise, the default ABI is `64'.

`-mmips-as'
     Generate code for the MIPS assembler, and invoke `mips-tfile' to
     add normal debug information.  This is the default for all
     platforms except for the OSF/1 reference platform, using the
     OSF/rose object format.  If the either of the `-gstabs' or
     `-gstabs+' switches are used, the `mips-tfile' program will
     encapsulate the stabs within MIPS ECOFF.

`-mgas'
     Generate code for the GNU assembler.  This is the default on the
     OSF/1 reference platform, using the OSF/rose object format.  Also,
     this is the default if the configure option `--with-gnu-as' is
     used.

`-msplit-addresses'
`-mno-split-addresses'
     Generate code to load the high and low parts of address constants
     separately.  This allows GCC to optimize away redundant loads of
     the high order bits of addresses.  This optimization requires GNU
     as and GNU ld.  This optimization is enabled by default for some
     embedded targets where GNU as and GNU ld are standard.

`-mrnames'
`-mno-rnames'
     The `-mrnames' switch says to output code using the MIPS software
     names for the registers, instead of the hardware names (ie, A0
     instead of $4).  The only known assembler that supports this option
     is the Algorithmics assembler.

`-mgpopt'
`-mno-gpopt'
     The `-mgpopt' switch says to write all of the data declarations
     before the instructions in the text section, this allows the MIPS
     assembler to generate one word memory references instead of using
     two words for short global or static data items.  This is on by
     default if optimization is selected.

`-mstats'
`-mno-stats'
     For each non-inline function processed, the `-mstats' switch
     causes the compiler to emit one line to the standard error file to
     print statistics about the program (number of registers saved,
     stack size, etc.).

`-mmemcpy'
`-mno-memcpy'
     The `-mmemcpy' switch makes all block moves call the appropriate
     string function (`memcpy' or `bcopy') instead of possibly
     generating inline code.

`-mmips-tfile'
`-mno-mips-tfile'
     The `-mno-mips-tfile' switch causes the compiler not postprocess
     the object file with the `mips-tfile' program, after the MIPS
     assembler has generated it to add debug support.  If `mips-tfile'
     is not run, then no local variables will be available to the
     debugger.  In addition, `stage2' and `stage3' objects will have
     the temporary file names passed to the assembler embedded in the
     object file, which means the objects will not compare the same.
     The `-mno-mips-tfile' switch should only be used when there are
     bugs in the `mips-tfile' program that prevents compilation.

`-msoft-float'
     Generate output containing library calls for floating point.
     *Warning:* the requisite libraries are not part of GCC.  Normally
     the facilities of the machine's usual C compiler are used, but
     this can't be done directly in cross-compilation.  You must make
     your own arrangements to provide suitable library functions for
     cross-compilation.

`-mhard-float'
     Generate output containing floating point instructions.  This is
     the default if you use the unmodified sources.

`-mabicalls'
`-mno-abicalls'
     Emit (or do not emit) the pseudo operations `.abicalls',
     `.cpload', and `.cprestore' that some System V.4 ports use for
     position independent code.

`-mlong-calls'
`-mno-long-calls'
     Do all calls with the `JALR' instruction, which requires loading
     up a function's address into a register before the call.  You need
     to use this switch, if you call outside of the current 512
     megabyte segment to functions that are not through pointers.

`-mhalf-pic'
`-mno-half-pic'
     Put pointers to extern references into the data section and load
     them up, rather than put the references in the text section.

`-membedded-pic'
`-mno-embedded-pic'
     Generate PIC code suitable for some embedded systems.  All calls
     are made using PC relative address, and all data is addressed
     using the $gp register.  No more than 65536 bytes of global data
     may be used.  This requires GNU as and GNU ld which do most of the
     work.  This currently only works on targets which use ECOFF; it
     does not work with ELF.

`-membedded-data'
`-mno-embedded-data'
     Allocate variables to the read-only data section first if
     possible, then next in the small data section if possible,
     otherwise in data.  This gives slightly slower code than the
     default, but reduces the amount of RAM required when executing,
     and thus may be preferred for some embedded systems.

`-muninit-const-in-rodata'
`-mno-uninit-const-in-rodata'
     When used together with `-membedded-data', it will always store
     uninitialized const variables in the read-only data section.

`-msingle-float'
`-mdouble-float'
     The `-msingle-float' switch tells gcc to assume that the floating
     point coprocessor only supports single precision operations, as on
     the `r4650' chip.  The `-mdouble-float' switch permits gcc to use
     double precision operations.  This is the default.

`-mmad'
`-mno-mad'
     Permit use of the `mad', `madu' and `mul' instructions, as on the
     `r4650' chip.

`-m4650'
     Turns on `-msingle-float', `-mmad', and, at least for now,
     `-mcpu=r4650'.

`-mips16'
`-mno-mips16'
     Enable 16-bit instructions.

`-mentry'
     Use the entry and exit pseudo ops.  This option can only be used
     with `-mips16'.

`-EL'
     Compile code for the processor in little endian mode.  The
     requisite libraries are assumed to exist.

`-EB'
     Compile code for the processor in big endian mode.  The requisite
     libraries are assumed to exist.

`-G NUM'
     Put global and static items less than or equal to NUM bytes into
     the small data or bss sections instead of the normal data or bss
     section.  This allows the assembler to emit one word memory
     reference instructions based on the global pointer (GP or $28),
     instead of the normal two words used.  By default, NUM is 8 when
     the MIPS assembler is used, and 0 when the GNU assembler is used.
     The `-G NUM' switch is also passed to the assembler and linker.
     All modules should be compiled with the same `-G NUM' value.

`-nocpp'
     Tell the MIPS assembler to not run its preprocessor over user
     assembler files (with a `.s' suffix) when assembling them.

`-mfix7000'
     Pass an option to gas which will cause nops to be inserted if the
     read of the destination register of an mfhi or mflo instruction
     occurs in the following two instructions.

`-no-crt0'
     Do not include the default crt0.

`-mflush-func=FUNC'
`-mno-flush-func'
     Specifies the function to call to flush the I and D caches, or to
     not call any such function.  If called, the function must take the
     same arguments as the common `_flush_func()', that is, the address
     of the memory range for which the cache is being flushed, the size
     of the memory range, and the number 3 (to flush both caches).  The
     default depends on the target gcc was configured for, but commonly
     is either `_flush_func' or `__cpu_flush'.

   These options are defined by the macro `TARGET_SWITCHES' in the
machine description.  The default for the options is also defined by
that macro, which enables you to change the defaults.


File: gcc.info,  Node: i386 and x86-64 Options,  Next: HPPA Options,  Prev: MIPS Options,  Up: Submodel Options

Intel 386 and AMD x86-64 Options
--------------------------------

   These `-m' options are defined for the i386 and x86-64 family of
computers:

`-mcpu=CPU-TYPE'
     Assume the defaults for the machine type CPU-TYPE when scheduling
     instructions.  The choices for CPU-TYPE are `i386', `i486',
     `i586', `i686', `pentium', `pentiumpro', `pentium4', `k6', and
     `athlon'

     While picking a specific CPU-TYPE will schedule things
     appropriately for that particular chip, the compiler will not
     generate any code that does not run on the i386 without the
     `-march=CPU-TYPE' option being used.  `i586' is equivalent to
     `pentium' and `i686' is equivalent to `pentiumpro'.  `k6' and
     `athlon' are the AMD chips as opposed to the Intel ones.

`-march=CPU-TYPE'
     Generate instructions for the machine type CPU-TYPE.  The choices
     for CPU-TYPE are the same as for `-mcpu'.  Moreover, specifying
     `-march=CPU-TYPE' implies `-mcpu=CPU-TYPE'.

`-m386'
`-m486'
`-mpentium'
`-mpentiumpro'
     These options are synonyms for `-mcpu=i386', `-mcpu=i486',
     `-mcpu=pentium', and `-mcpu=pentiumpro' respectively.  These
     synonyms are deprecated.

`-mintel-syntax'
     Emit assembly using Intel syntax opcodes instead of AT&T syntax.

`-mieee-fp'
`-mno-ieee-fp'
     Control whether or not the compiler uses IEEE floating point
     comparisons.  These handle correctly the case where the result of a
     comparison is unordered.

`-msoft-float'
     Generate output containing library calls for floating point.
     *Warning:* the requisite libraries are not part of GCC.  Normally
     the facilities of the machine's usual C compiler are used, but
     this can't be done directly in cross-compilation.  You must make
     your own arrangements to provide suitable library functions for
     cross-compilation.

     On machines where a function returns floating point results in the
     80387 register stack, some floating point opcodes may be emitted
     even if `-msoft-float' is used.

`-mno-fp-ret-in-387'
     Do not use the FPU registers for return values of functions.

     The usual calling convention has functions return values of types
     `float' and `double' in an FPU register, even if there is no FPU.
     The idea is that the operating system should emulate an FPU.

     The option `-mno-fp-ret-in-387' causes such values to be returned
     in ordinary CPU registers instead.

`-mno-fancy-math-387'
     Some 387 emulators do not support the `sin', `cos' and `sqrt'
     instructions for the 387.  Specify this option to avoid generating
     those instructions.  This option is the default on FreeBSD.  As of
     revision 2.6.1, these instructions are not generated unless you
     also use the `-funsafe-math-optimizations' switch.

`-malign-double'
`-mno-align-double'
     Control whether GCC aligns `double', `long double', and `long
     long' variables on a two word boundary or a one word boundary.
     Aligning `double' variables on a two word boundary will produce
     code that runs somewhat faster on a `Pentium' at the expense of
     more memory.

`-m128bit-long-double'
     Control the size of `long double' type. i386 application binary
     interface specify the size to be 12 bytes, while modern
     architectures (Pentium and newer) prefer `long double' aligned to
     8 or 16 byte boundary.  This is impossible to reach with 12 byte
     long doubles in the array accesses.

     *Warning:* if you use the `-m128bit-long-double' switch, the
     structures and arrays containing `long double' will change their
     size as well as function calling convention for function taking
     `long double' will be modified.

`-m96bit-long-double'
     Set the size of `long double' to 96 bits as required by the i386
     application binary interface.  This is the default.

`-msvr3-shlib'
`-mno-svr3-shlib'
     Control whether GCC places uninitialized local variables into the
     `bss' or `data' segments.  `-msvr3-shlib' places them into `bss'.
     These options are meaningful only on System V Release 3.

`-mrtd'
     Use a different function-calling convention, in which functions
     that take a fixed number of arguments return with the `ret' NUM
     instruction, which pops their arguments while returning.  This
     saves one instruction in the caller since there is no need to pop
     the arguments there.

     You can specify that an individual function is called with this
     calling sequence with the function attribute `stdcall'.  You can
     also override the `-mrtd' option by using the function attribute
     `cdecl'.  *Note Function Attributes::.

     *Warning:* this calling convention is incompatible with the one
     normally used on Unix, so you cannot use it if you need to call
     libraries compiled with the Unix compiler.

     Also, you must provide function prototypes for all functions that
     take variable numbers of arguments (including `printf'); otherwise
     incorrect code will be generated for calls to those functions.

     In addition, seriously incorrect code will result if you call a
     function with too many arguments.  (Normally, extra arguments are
     harmlessly ignored.)

`-mregparm=NUM'
     Control how many registers are used to pass integer arguments.  By
     default, no registers are used to pass arguments, and at most 3
     registers can be used.  You can control this behavior for a
     specific function by using the function attribute `regparm'.
     *Note Function Attributes::.

     *Warning:* if you use this switch, and NUM is nonzero, then you
     must build all modules with the same value, including any
     libraries.  This includes the system libraries and startup modules.

`-mpreferred-stack-boundary=NUM'
     Attempt to keep the stack boundary aligned to a 2 raised to NUM
     byte boundary.  If `-mpreferred-stack-boundary' is not specified,
     the default is 4 (16 bytes or 128 bits), except when optimizing
     for code size (`-Os'), in which case the default is the minimum
     correct alignment (4 bytes for x86, and 8 bytes for x86-64).

     On Pentium and PentiumPro, `double' and `long double' values
     should be aligned to an 8 byte boundary (see `-malign-double') or
     suffer significant run time performance penalties.  On Pentium
     III, the Streaming SIMD Extension (SSE) data type `__m128' suffers
     similar penalties if it is not 16 byte aligned.

     To ensure proper alignment of this values on the stack, the stack
     boundary must be as aligned as that required by any value stored
     on the stack.  Further, every function must be generated such that
     it keeps the stack aligned.  Thus calling a function compiled with
     a higher preferred stack boundary from a function compiled with a
     lower preferred stack boundary will most likely misalign the
     stack.  It is recommended that libraries that use callbacks always
     use the default setting.

     This extra alignment does consume extra stack space, and generally
     increases code size.  Code that is sensitive to stack space usage,
     such as embedded systems and operating system kernels, may want to
     reduce the preferred alignment to `-mpreferred-stack-boundary=2'.

`-mmmx'
`-mno-mmx'

`-msse'
`-mno-sse'

`-m3dnow'
`-mno-3dnow'
     These switches enable or disable the use of built-in functions
     that allow direct access to the MMX, SSE and 3Dnow extensions of
     the instruction set.

     The following machine modes are available for use with MMX
     built-in functions (*note Vector Extensions::): `V2SI' for a
     vector of two 32 bit integers, `V4HI' for a vector of four 16 bit
     integers, and `V8QI' for a vector of eight 8 bit integers.  Some
     of the built-in functions operate on MMX registers as a whole 64
     bit entity, these use `DI' as their mode.

     If 3Dnow extensions are enabled, `V2SF' is used as a mode for a
     vector of two 32 bit floating point values.

     If SSE extensions are enabled, `V4SF' is used for a vector of four
     32 bit floating point values.  Some instructions use a vector of
     four 32 bit integers, these use `V4SI'.  Finally, some
     instructions operate on an entire vector register, interpreting it
     as a 128 bit integer, these use mode `TI'.

     The following built-in functions are made available by `-mmmx':
    `v8qi __builtin_ia32_paddb (v8qi, v8qi)'
          Generates the `paddb' machine instruction.

    `v4hi __builtin_ia32_paddw (v4hi, v4hi)'
          Generates the `paddw' machine instruction.

    `v2si __builtin_ia32_paddd (v2si, v2si)'
          Generates the `paddd' machine instruction.

    `v8qi __builtin_ia32_psubb (v8qi, v8qi)'
          Generates the `psubb' machine instruction.

    `v4hi __builtin_ia32_psubw (v4hi, v4hi)'
          Generates the `psubw' machine instruction.

    `v2si __builtin_ia32_psubd (v2si, v2si)'
          Generates the `psubd' machine instruction.

    `v8qi __builtin_ia32_paddsb (v8qi, v8qi)'
          Generates the `paddsb' machine instruction.

    `v4hi __builtin_ia32_paddsw (v4hi, v4hi)'
          Generates the `paddsw' machine instruction.

    `v8qi __builtin_ia32_psubsb (v8qi, v8qi)'
          Generates the `psubsb' machine instruction.

    `v4hi __builtin_ia32_psubsw (v4hi, v4hi)'
          Generates the `psubsw' machine instruction.

    `v8qi __builtin_ia32_paddusb (v8qi, v8qi)'
          Generates the `paddusb' machine instruction.

    `v4hi __builtin_ia32_paddusw (v4hi, v4hi)'
          Generates the `paddusw' machine instruction.

    `v8qi __builtin_ia32_psubusb (v8qi, v8qi)'
          Generates the `psubusb' machine instruction.

    `v4hi __builtin_ia32_psubusw (v4hi, v4hi)'
          Generates the `psubusw' machine instruction.

    `v4hi __builtin_ia32_pmullw (v4hi, v4hi)'
          Generates the `pmullw' machine instruction.

    `v4hi __builtin_ia32_pmulhw (v4hi, v4hi)'
          Generates the `pmulhw' machine instruction.

    `di __builtin_ia32_pand (di, di)'
          Generates the `pand' machine instruction.

    `di __builtin_ia32_pandn (di,di)'
          Generates the `pandn' machine instruction.

    `di __builtin_ia32_por (di, di)'
          Generates the `por' machine instruction.

    `di __builtin_ia32_pxor (di, di)'
          Generates the `pxor' machine instruction.

    `v8qi __builtin_ia32_pcmpeqb (v8qi, v8qi)'
          Generates the `pcmpeqb' machine instruction.

    `v4hi __builtin_ia32_pcmpeqw (v4hi, v4hi)'
          Generates the `pcmpeqw' machine instruction.

    `v2si __builtin_ia32_pcmpeqd (v2si, v2si)'
          Generates the `pcmpeqd' machine instruction.

    `v8qi __builtin_ia32_pcmpgtb (v8qi, v8qi)'
          Generates the `pcmpgtb' machine instruction.

    `v4hi __builtin_ia32_pcmpgtw (v4hi, v4hi)'
          Generates the `pcmpgtw' machine instruction.

    `v2si __builtin_ia32_pcmpgtd (v2si, v2si)'
          Generates the `pcmpgtd' machine instruction.

    `v8qi __builtin_ia32_punpckhbw (v8qi, v8qi)'
          Generates the `punpckhbw' machine instruction.

    `v4hi __builtin_ia32_punpckhwd (v4hi, v4hi)'
          Generates the `punpckhwd' machine instruction.

    `v2si __builtin_ia32_punpckhdq (v2si, v2si)'
          Generates the `punpckhdq' machine instruction.

    `v8qi __builtin_ia32_punpcklbw (v8qi, v8qi)'
          Generates the `punpcklbw' machine instruction.

    `v4hi __builtin_ia32_punpcklwd (v4hi, v4hi)'
          Generates the `punpcklwd' machine instruction.

    `v2si __builtin_ia32_punpckldq (v2si, v2si)'
          Generates the `punpckldq' machine instruction.

    `v8qi __builtin_ia32_packsswb (v4hi, v4hi)'
          Generates the `packsswb' machine instruction.

    `v4hi __builtin_ia32_packssdw (v2si, v2si)'
          Generates the `packssdw' machine instruction.

    `v8qi __builtin_ia32_packuswb (v4hi, v4hi)'
          Generates the `packuswb' machine instruction.

     The following built-in functions are made available either with
     `-msse', or with a combination of `-m3dnow' and `-march=athlon'.
    `v4hi __builtin_ia32_pmulhuw (v4hi, v4hi)'
          Generates the `pmulhuw' machine instruction.

    `v8qi __builtin_ia32_pavgb (v8qi, v8qi)'
          Generates the `pavgb' machine instruction.

    `v4hi __builtin_ia32_pavgw (v4hi, v4hi)'
          Generates the `pavgw' machine instruction.

    `v4hi __builtin_ia32_psadbw (v8qi, v8qi)'
          Generates the `psadbw' machine instruction.

    `v8qi __builtin_ia32_pmaxub (v8qi, v8qi)'
          Generates the `pmaxub' machine instruction.

    `v4hi __builtin_ia32_pmaxsw (v4hi, v4hi)'
          Generates the `pmaxsw' machine instruction.

    `v8qi __builtin_ia32_pminub (v8qi, v8qi)'
          Generates the `pminub' machine instruction.

    `v4hi __builtin_ia32_pminsw (v4hi, v4hi)'
          Generates the `pminsw' machine instruction.

    `int __builtin_ia32_pextrw (v4hi, int)'
          Generates the `pextrw' machine instruction.

    `v4hi __builtin_ia32_pinsrw (v4hi, int, int)'
          Generates the `pinsrw' machine instruction.

    `int __builtin_ia32_pmovmskb (v8qi)'
          Generates the `pmovmskb' machine instruction.

    `void __builtin_ia32_maskmovq (v8qi, v8qi, char *)'
          Generates the `maskmovq' machine instruction.

    `void __builtin_ia32_movntq (di *, di)'
          Generates the `movntq' machine instruction.

    `void __builtin_ia32_sfence (void)'
          Generates the `sfence' machine instruction.

    `void __builtin_ia32_prefetch (char *, int selector)'
          Generates a prefetch machine instruction, depending on the
          value of selector.  If `selector' is 0, it generates
          `prefetchnta'; for a value of 1, it generates `prefetcht0';
          for a value of 2, it generates `prefetcht1'; and for a value
          of 3 it generates `prefetcht2'.

     The following built-in functions are available when `-msse' is
     used.

    `int __builtin_ia32_comieq (v4sf, v4sf)'
          Generates the `comiss' machine instruction and performs an
          equality comparison.  The return value is the truth value of
          that comparison.

    `int __builtin_ia32_comineq (v4sf, v4sf)'
          Generates the `comiss' machine instruction and performs an
          inequality comparison.  The return value is the truth value
          of that comparison.

    `int __builtin_ia32_comilt (v4sf, v4sf)'
          Generates the `comiss' machine instruction and performs a
          "less than" comparison.  The return value is the truth value
          of that comparison.

    `int __builtin_ia32_comile (v4sf, v4sf)'
          Generates the `comiss' machine instruction and performs a
          "less or equal" comparison.  The return value is the truth
          value of that comparison.

    `int __builtin_ia32_comigt (v4sf, v4sf)'
          Generates the `comiss' machine instruction and performs a
          "greater than" comparison.  The return value is the truth
          value of that comparison.

    `int __builtin_ia32_comige (v4sf, v4sf)'
          Generates the `comiss' machine instruction and performs a
          "greater or equal" comparison.  The return value is the truth
          value of that comparison.

    `int __builtin_ia32_ucomieq (v4sf, v4sf)'
          Generates the `ucomiss' machine instruction and performs an
          equality comparison.  The return value is the truth value of
          that comparison.

    `int __builtin_ia32_ucomineq (v4sf, v4sf)'
          Generates the `ucomiss' machine instruction and performs an
          inequality comparison.  The return value is the truth value
          of that comparison.

    `int __builtin_ia32_ucomilt (v4sf, v4sf)'
          Generates the `ucomiss' machine instruction and performs a
          "less than" comparison.  The return value is the truth value
          of that comparison.

    `int __builtin_ia32_ucomile (v4sf, v4sf)'
          Generates the `ucomiss' machine instruction and performs a
          "less or equal" comparison.  The return value is the truth
          value of that comparison.

    `int __builtin_ia32_ucomigt (v4sf, v4sf)'
          Generates the `ucomiss' machine instruction and performs a
          "greater than" comparison.  The return value is the truth
          value of that comparison.

    `int __builtin_ia32_ucomige (v4sf, v4sf)'
          Generates the `ucomiss' machine instruction and performs a
          "greater or equal" comparison.  The return value is the truth
          value of that comparison.

    `v4sf __builtin_ia32_addps (v4sf, v4sf)'
          Generates the `addps' machine instruction.

    `v4sf __builtin_ia32_addss (v4sf, v4sf)'
          Generates the `addss' machine instruction.

    `v4sf __builtin_ia32_subps (v4sf, v4sf)'
          Generates the `subps' machine instruction.

    `v4sf __builtin_ia32_subss (v4sf, v4sf)'
          Generates the `subss' machine instruction.

    `v4sf __builtin_ia32_mulps (v4sf, v4sf)'
          Generates the `mulps' machine instruction.

    `v4sf __builtin_ia32_mulss (v4sf, v4sf)'
          Generates the `mulss' machine instruction.

    `v4sf __builtin_ia32_divps (v4sf, v4sf)'
          Generates the `divps' machine instruction.

    `v4sf __builtin_ia32_divss (v4sf, v4sf)'
          Generates the `divss' machine instruction.

    `v4si __builtin_ia32_cmpeqps (v4sf, v4sf)'
          Generates the `cmpeqps' machine instruction.

    `v4si __builtin_ia32_cmplts (v4sf, v4sf)'
          Generates the `cmpltps' machine instruction.

    `v4si __builtin_ia32_cmpleps (v4sf, v4sf)'
          Generates the `cmpleps' machine instruction.

    `v4si __builtin_ia32_cmpgtps (v4sf, v4sf)'
          Generates the `cmpgtps' machine instruction.

    `v4si __builtin_ia32_cmpgeps (v4sf, v4sf)'
          Generates the `cmpgeps' machine instruction.

    `v4si __builtin_ia32_cmpunordps (v4sf, v4sf)'
          Generates the `cmpunodps' machine instruction.

    `v4si __builtin_ia32_cmpneqps (v4sf, v4sf)'
          Generates the `cmpeqps' machine instruction.

    `v4si __builtin_ia32_cmpnltps (v4sf, v4sf)'
          Generates the `cmpltps' machine instruction.

    `v4si __builtin_ia32_cmpnleps (v4sf, v4sf)'
          Generates the `cmpleps' machine instruction.

    `v4si __builtin_ia32_cmpngtps (v4sf, v4sf)'
          Generates the `cmpgtps' machine instruction.

    `v4si __builtin_ia32_cmpngeps (v4sf, v4sf)'
          Generates the `cmpgeps' machine instruction.

    `v4si __builtin_ia32_cmpordps (v4sf, v4sf)'
          Generates the `cmpunodps' machine instruction.

    `v4si __builtin_ia32_cmpeqss (v4sf, v4sf)'
          Generates the `cmpeqss' machine instruction.

    `v4si __builtin_ia32_cmpltss (v4sf, v4sf)'
          Generates the `cmpltss' machine instruction.

    `v4si __builtin_ia32_cmpless (v4sf, v4sf)'
          Generates the `cmpless' machine instruction.

    `v4si __builtin_ia32_cmpgtss (v4sf, v4sf)'
          Generates the `cmpgtss' machine instruction.

    `v4si __builtin_ia32_cmpgess (v4sf, v4sf)'
          Generates the `cmpgess' machine instruction.

    `v4si __builtin_ia32_cmpunordss (v4sf, v4sf)'
          Generates the `cmpunodss' machine instruction.

    `v4si __builtin_ia32_cmpneqss (v4sf, v4sf)'
          Generates the `cmpeqss' machine instruction.

    `v4si __builtin_ia32_cmpnlts (v4sf, v4sf)'
          Generates the `cmpltss' machine instruction.

    `v4si __builtin_ia32_cmpnless (v4sf, v4sf)'
          Generates the `cmpless' machine instruction.

    `v4si __builtin_ia32_cmpngtss (v4sf, v4sf)'
          Generates the `cmpgtss' machine instruction.

    `v4si __builtin_ia32_cmpngess (v4sf, v4sf)'
          Generates the `cmpgess' machine instruction.

    `v4si __builtin_ia32_cmpordss (v4sf, v4sf)'
          Generates the `cmpunodss' machine instruction.

    `v4sf __builtin_ia32_maxps (v4sf, v4sf)'
          Generates the `maxps' machine instruction.

    `v4sf __builtin_ia32_maxsss (v4sf, v4sf)'
          Generates the `maxss' machine instruction.

    `v4sf __builtin_ia32_minps (v4sf, v4sf)'
          Generates the `minps' machine instruction.

    `v4sf __builtin_ia32_minsss (v4sf, v4sf)'
          Generates the `minss' machine instruction.

    `ti __builtin_ia32_andps (ti, ti)'
          Generates the `andps' machine instruction.

    `ti __builtin_ia32_andnps (ti, ti)'
          Generates the `andnps' machine instruction.

    `ti __builtin_ia32_orps (ti, ti)'
          Generates the `orps' machine instruction.

    `ti __builtin_ia32_xorps (ti, ti)'
          Generates the `xorps' machine instruction.

    `v4sf __builtin_ia32_movps (v4sf, v4sf)'
          Generates the `movps' machine instruction.

    `v4sf __builtin_ia32_movhlps (v4sf, v4sf)'
          Generates the `movhlps' machine instruction.

    `v4sf __builtin_ia32_movlhps (v4sf, v4sf)'
          Generates the `movlhps' machine instruction.

    `v4sf __builtin_ia32_unpckhps (v4sf, v4sf)'
          Generates the `unpckhps' machine instruction.

    `v4sf __builtin_ia32_unpcklps (v4sf, v4sf)'
          Generates the `unpcklps' machine instruction.

    `v4sf __builtin_ia32_cvtpi2ps (v4sf, v2si)'
          Generates the `cvtpi2ps' machine instruction.

    `v2si __builtin_ia32_cvtps2pi (v4sf)'
          Generates the `cvtps2pi' machine instruction.

    `v4sf __builtin_ia32_cvtsi2ss (v4sf, int)'
          Generates the `cvtsi2ss' machine instruction.

    `int __builtin_ia32_cvtss2si (v4sf)'
          Generates the `cvtsi2ss' machine instruction.

    `v2si __builtin_ia32_cvttps2pi (v4sf)'
          Generates the `cvttps2pi' machine instruction.

    `int __builtin_ia32_cvttss2si (v4sf)'
          Generates the `cvttsi2ss' machine instruction.

    `v4sf __builtin_ia32_rcpps (v4sf)'
          Generates the `rcpps' machine instruction.

    `v4sf __builtin_ia32_rsqrtps (v4sf)'
          Generates the `rsqrtps' machine instruction.

    `v4sf __builtin_ia32_sqrtps (v4sf)'
          Generates the `sqrtps' machine instruction.

    `v4sf __builtin_ia32_rcpss (v4sf)'
          Generates the `rcpss' machine instruction.

    `v4sf __builtin_ia32_rsqrtss (v4sf)'
          Generates the `rsqrtss' machine instruction.

    `v4sf __builtin_ia32_sqrtss (v4sf)'
          Generates the `sqrtss' machine instruction.

    `v4sf __builtin_ia32_shufps (v4sf, v4sf, int)'
          Generates the `shufps' machine instruction.

    `v4sf __builtin_ia32_loadaps (float *)'
          Generates the `movaps' machine instruction as a load from
          memory.

    `void __builtin_ia32_storeaps (float *, v4sf)'
          Generates the `movaps' machine instruction as a store to
          memory.

    `v4sf __builtin_ia32_loadups (float *)'
          Generates the `movups' machine instruction as a load from
          memory.

    `void __builtin_ia32_storeups (float *, v4sf)'
          Generates the `movups' machine instruction as a store to
          memory.

    `v4sf __builtin_ia32_loadsss (float *)'
          Generates the `movss' machine instruction as a load from
          memory.

    `void __builtin_ia32_storess (float *, v4sf)'
          Generates the `movss' machine instruction as a store to
          memory.

    `v4sf __builtin_ia32_loadhps (v4sf, v2si *)'
          Generates the `movhps' machine instruction as a load from
          memory.

    `v4sf __builtin_ia32_loadlps (v4sf, v2si *)'
          Generates the `movlps' machine instruction as a load from
          memory

    `void __builtin_ia32_storehps (v4sf, v2si *)'
          Generates the `movhps' machine instruction as a store to
          memory.

    `void __builtin_ia32_storelps (v4sf, v2si *)'
          Generates the `movlps' machine instruction as a store to
          memory.

    `void __builtin_ia32_movntps (float *, v4sf)'
          Generates the `movntps' machine instruction.

    `int __builtin_ia32_movmskps (v4sf)'
          Generates the `movntps' machine instruction.

    `void __builtin_ia32_storeps1 (float *, v4sf)'
          Generates the `movaps' machine instruction as a store to
          memory.  Before storing, the value is modified with a
          `shufps' instruction so that the lowest of the four floating
          point elements is replicated across the entire vector that is
          stored.

    `void __builtin_ia32_storerps (float *, v4sf)'
          Generates the `movaps' machine instruction as a store to
          memory.  Before storing, the value is modified with a
          `shufps' instruction so that the order of the four floating
          point elements in the vector is reversed.

    `v4sf __builtin_ia32_loadps1 (float *)'
          Generates a `movss' machine instruction to load a floating
          point value from memory, and a `shufps' instruction to
          replicate the loaded value across all four elements of the
          result vector.

    `v4sf __builtin_ia32_loadrps (float *)'
          Generates a `movaps' machine instruction to load a vector from
          memory, and a `shufps' instruction to reverse the order of the
          four floating point elements in the result vector.

    `v4sf __builtin_ia32_setps (float, float, float, float)'
          Constructs a vector from four single floating point values.
          The return value is equal to the value that would result from
          storing the four arguments into consecutive memory locations
          and then executing a `movaps' to load the vector from memory.

    `v4sf __builtin_ia32_setps1 (float)'
          Constructs a vector from a single floating point value by
          replicating it across all four elements of the result vector.

`-mpush-args'
`-mno-push-args'
     Use PUSH operations to store outgoing parameters.  This method is
     shorter and usually equally fast as method using SUB/MOV
     operations and is enabled by default.  In some cases disabling it
     may improve performance because of improved scheduling and reduced
     dependencies.

`-maccumulate-outgoing-args'
     If enabled, the maximum amount of space required for outgoing
     arguments will be computed in the function prologue.  This is
     faster on most modern CPUs because of reduced dependencies,
     improved scheduling and reduced stack usage when preferred stack
     boundary is not equal to 2.  The drawback is a notable increase in
     code size.  This switch implies `-mno-push-args'.

`-mthreads'
     Support thread-safe exception handling on `Mingw32'.  Code that
     relies on thread-safe exception handling must compile and link all
     code with the `-mthreads' option.  When compiling, `-mthreads'
     defines `-D_MT'; when linking, it links in a special thread helper
     library `-lmingwthrd' which cleans up per thread exception
     handling data.

`-mno-align-stringops'
     Do not align destination of inlined string operations.  This
     switch reduces code size and improves performance in case the
     destination is already aligned, but gcc don't know about it.

`-minline-all-stringops'
     By default GCC inlines string operations only when destination is
     known to be aligned at least to 4 byte boundary.  This enables
     more inlining, increase code size, but may improve performance of
     code that depends on fast memcpy, strlen and memset for short
     lengths.

`-momit-leaf-frame-pointer'
     Don't keep the frame pointer in a register for leaf functions.
     This avoids the instructions to save, set up and restore frame
     pointers and makes an extra register available in leaf functions.
     The option `-fomit-frame-pointer' removes the frame pointer for
     all functions which might make debugging harder.

   These `-m' switches are supported in addition to the above on AMD
x86-64 processors in 64-bit environments.

`-m32'
`-m64'
     Generate code for a 32-bit or 64-bit environment.  The 32-bit
     environment sets int, long and pointer to 32 bits and generates
     code that runs on any i386 system.  The 64-bit environment sets
     int to 32 bits and long and pointer to 64 bits and generates code
     for AMD's x86-64 architecture.

`-mno-red-zone'
     Do not use a so called red zone for x86-64 code.  The red zone is
     mandated by the x86-64 ABI, it is a 128-byte area beyond the
     location of the stack pointer that will not be modified by signal
     or interrupt handlers and therefore can be used for temporary data
     without adjusting the stack pointer.  The flag `-mno-red-zone'
     disables this red zone.


File: gcc.info,  Node: HPPA Options,  Next: Intel 960 Options,  Prev: i386 and x86-64 Options,  Up: Submodel Options

HPPA Options
------------

   These `-m' options are defined for the HPPA family of computers:

`-march=ARCHITECTURE-TYPE'
     Generate code for the specified architecture.  The choices for
     ARCHITECTURE-TYPE are `1.0' for PA 1.0, `1.1' for PA 1.1, and
     `2.0' for PA 2.0 processors.  Refer to `/usr/lib/sched.models' on
     an HP-UX system to determine the proper architecture option for
     your machine.  Code compiled for lower numbered architectures will
     run on higher numbered architectures, but not the other way around.

     PA 2.0 support currently requires gas snapshot 19990413 or later.
     The next release of binutils (current is 2.9.1) will probably
     contain PA 2.0 support.

`-mpa-risc-1-0'
`-mpa-risc-1-1'
`-mpa-risc-2-0'
     Synonyms for `-march=1.0', `-march=1.1', and `-march=2.0'
     respectively.

`-mbig-switch'
     Generate code suitable for big switch tables.  Use this option
     only if the assembler/linker complain about out of range branches
     within a switch table.

`-mjump-in-delay'
     Fill delay slots of function calls with unconditional jump
     instructions by modifying the return pointer for the function call
     to be the target of the conditional jump.

`-mdisable-fpregs'
     Prevent floating point registers from being used in any manner.
     This is necessary for compiling kernels which perform lazy context
     switching of floating point registers.  If you use this option and
     attempt to perform floating point operations, the compiler will
     abort.

`-mdisable-indexing'
     Prevent the compiler from using indexing address modes.  This
     avoids some rather obscure problems when compiling MIG generated
     code under MACH.

`-mno-space-regs'
     Generate code that assumes the target has no space registers.
     This allows GCC to generate faster indirect calls and use unscaled
     index address modes.

     Such code is suitable for level 0 PA systems and kernels.

`-mfast-indirect-calls'
     Generate code that assumes calls never cross space boundaries.
     This allows GCC to emit code which performs faster indirect calls.

     This option will not work in the presence of shared libraries or
     nested functions.

`-mlong-load-store'
     Generate 3-instruction load and store sequences as sometimes
     required by the HP-UX 10 linker.  This is equivalent to the `+k'
     option to the HP compilers.

`-mportable-runtime'
     Use the portable calling conventions proposed by HP for ELF
     systems.

`-mgas'
     Enable the use of assembler directives only GAS understands.

`-mschedule=CPU-TYPE'
     Schedule code according to the constraints for the machine type
     CPU-TYPE.  The choices for CPU-TYPE are `700' `7100', `7100LC',
     `7200', and `8000'.  Refer to `/usr/lib/sched.models' on an HP-UX
     system to determine the proper scheduling option for your machine.

`-mlinker-opt'
     Enable the optimization pass in the HPUX linker.  Note this makes
     symbolic debugging impossible.  It also triggers a bug in the HPUX
     8 and HPUX 9 linkers in which they give bogus error messages when
     linking some programs.

`-msoft-float'
     Generate output containing library calls for floating point.
     *Warning:* the requisite libraries are not available for all HPPA
     targets.  Normally the facilities of the machine's usual C
     compiler are used, but this cannot be done directly in
     cross-compilation.  You must make your own arrangements to provide
     suitable library functions for cross-compilation.  The embedded
     target `hppa1.1-*-pro' does provide software floating point
     support.

     `-msoft-float' changes the calling convention in the output file;
     therefore, it is only useful if you compile _all_ of a program with
     this option.  In particular, you need to compile `libgcc.a', the
     library that comes with GCC, with `-msoft-float' in order for this
     to work.


File: gcc.info,  Node: Intel 960 Options,  Next: DEC Alpha Options,  Prev: HPPA Options,  Up: Submodel Options

Intel 960 Options
-----------------

   These `-m' options are defined for the Intel 960 implementations:

`-mCPU-TYPE'
     Assume the defaults for the machine type CPU-TYPE for some of the
     other options, including instruction scheduling, floating point
     support, and addressing modes.  The choices for CPU-TYPE are `ka',
     `kb', `mc', `ca', `cf', `sa', and `sb'.  The default is `kb'.

`-mnumerics'
`-msoft-float'
     The `-mnumerics' option indicates that the processor does support
     floating-point instructions.  The `-msoft-float' option indicates
     that floating-point support should not be assumed.

`-mleaf-procedures'
`-mno-leaf-procedures'
     Do (or do not) attempt to alter leaf procedures to be callable
     with the `bal' instruction as well as `call'.  This will result in
     more efficient code for explicit calls when the `bal' instruction
     can be substituted by the assembler or linker, but less efficient
     code in other cases, such as calls via function pointers, or using
     a linker that doesn't support this optimization.

`-mtail-call'
`-mno-tail-call'
     Do (or do not) make additional attempts (beyond those of the
     machine-independent portions of the compiler) to optimize
     tail-recursive calls into branches.  You may not want to do this
     because the detection of cases where this is not valid is not
     totally complete.  The default is `-mno-tail-call'.

`-mcomplex-addr'
`-mno-complex-addr'
     Assume (or do not assume) that the use of a complex addressing
     mode is a win on this implementation of the i960.  Complex
     addressing modes may not be worthwhile on the K-series, but they
     definitely are on the C-series.  The default is currently
     `-mcomplex-addr' for all processors except the CB and CC.

`-mcode-align'
`-mno-code-align'
     Align code to 8-byte boundaries for faster fetching (or don't
     bother).  Currently turned on by default for C-series
     implementations only.

`-mic-compat'
`-mic2.0-compat'
`-mic3.0-compat'
     Enable compatibility with iC960 v2.0 or v3.0.

`-masm-compat'
`-mintel-asm'
     Enable compatibility with the iC960 assembler.

`-mstrict-align'
`-mno-strict-align'
     Do not permit (do permit) unaligned accesses.

`-mold-align'
     Enable structure-alignment compatibility with Intel's gcc release
     version 1.3 (based on gcc 1.37).  This option implies
     `-mstrict-align'.

`-mlong-double-64'
     Implement type `long double' as 64-bit floating point numbers.
     Without the option `long double' is implemented by 80-bit floating
     point numbers.  The only reason we have it because there is no
     128-bit `long double' support in `fp-bit.c' yet.  So it is only
     useful for people using soft-float targets.  Otherwise, we should
     recommend against use of it.

