;; UNIVAC 1107 -- 1962, EXEC I
;; UNIVAC 1108 -- 1965/66, EXEC 8
;; UNIVAC 1106 -- 1969, EXEC 8
;; UNIVAC 1106/II -- 1975, EXEC 8
;; UNIVAC 1110 -- 1972
;; Sperry Univac 1100/20 = UNIVAC 1106
;; Sperry Univac 1100/40 = UNIVAC 1110
;; Sperry Univac 1100/11, /12, /21, /22, /4x -- 1975
;; Sperry Univac 1100/181 -- 1976
;; Sperry Univac 1100/80, /81, /82 -- 1976
;; Sperry Univac 1100/83, /84 -- 1977
;; Sperry Univac 1100/60, /60 AVP, /61, /61 B1 -- 1979, Motorola 10800 CPU
;; Sperry Univac 1100/62-H1, -H2 -- 1979, Motorola 10800 CPU
;; Sperry Univac 1100/62-E1, -E2 -- 1980, Motorola 10800 CPU
;; Sperry Univac 1100/63, /64 -- 1981, Motorola 10800 CPU
;; Sperry Univac 1100/91, /92, /93, /94 -- 1982
;; Sperry Univac 1100/70 -- 1983
;; Unisys 2200 -- 1986
;; Sperry Univac 1100/90 II -- 1987
;; Sperry Univac 1100/91 II SV -- 1987
;; Sperry Univac 1100/92 II SV -- 1987
;; Unisys 1100/94 II Turbo -- 1987/89, OS/1100
;; Sperry Univac 2200/201, /202, /203, /204 -- 1986
;; Unisys 2200/400 -- 1988
;; Unisys 2200/600, /644 -- 1988, OS/1100
;; Unisys 2200/600 ES -- 1990, OS/1100
;; Unisys 2200/100 -- 1990, OS/1100
;; Unisys 2200/900 -- 1991/92, ECL, OS/1100
;; Unisys 2200/500 -- 1993, CMOS
;; Unisys ClearPath -- 1996
;; Unisys ClearPath/2200
;; Unisys ClearPath HMP IX5000 -- 1998
;; Unisys ClearPath IX5600
;; Unisys ClearPath IX5800
;; Unisys ClearPath IX6600
;; Unisys ClearPath IX6800 -- 1999
;; Unisys ClearPath IE

;; Borroughs B5000 -- 1961
;; Borroughs A Series -- 1981
;; Unisys A1, A4, A6 -- 1987

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Data Movement

(define_insn "movsi"
  [(set (match_operand:SI 0 "acc_or_mem_operand" "=a,m,x,m,R,m,am")
	(match_operand:SI 1 "general_operand" "am,a,axm,x,am,R,O"))
  ""
  "@
   LA %0,%1
   SA %1,%0
   LX %0,%1
   SX %1,%0
   LR %0,%1
   SR %1,%0
   SZ %0")

(define_insn "movdi"
  [(set (match_operand:DI 0 "acc_or_mem_operand" "=a,m")
	(match_operand:DI 1 "acc_or_mem_operand" "am,a"))
  ""
  "@
   DL %0,%1
   DS %0,%1")


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Integer Arithmetic

(define_insn "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=a,x")
	(plus:SI (match_operand:SI 1 "register_operand" "%0,0")
		 (match_operand:SI 2 "reg_or_mem_operand" "am,xm")))]
  ""
  "@
   AA %0,%2
   AX %0,%2")

(define_insn "AMA"
  [(set (match_operand:SI 0 "accumulator_operand" "=a")
	(plus:SI (match_operand:SI 1 "accumulator_operand" "0")
		 (abs:SI (match_operand:SI 2 "acc_or_mem_operand" "am"))))]
  ""
  "AMA %0,%2")

(define_insn "ANMA"
  [(set (match_operand:SI 0 "accumulator_operand" "=a")
	(plus:SI (match_operand:SI 1 "accumulator_operand" "0")
		 (neg:SI
		  (abs:SI (match_operand:SI 2 "acc_or_mem_operand" "am")))))]
  ""
  "ANMA %0,%2")

(define_insn "adddi3"
  [(set (match_operand:DI 0 "accumulator_operand" "=a")
	(plus:DI (match_operand:DI 1 "accumulator_operand" "%0")
		 (match_operand:DI 2 "acc_or_mem_operand" "am")))]
  ""
  "DA %0,%2")

(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=a,x")
	(minus:SI (match_operand:SI 1 "register_operand" "0,0")
		  (match_operand:SI 2 "reg_or_mem_operand" "am,xm")))]
  ""
  "@
   ANA %0,%2
   ANX %0,%2")

(define_insn "subdi3"
  [(set (match_operand:DI 0 "accumulator_operand" "=a")
	(minus:DI (match_operand:DI 1 "accumulator_operand" "%0")
		  (match_operand:DI 2 "acc_or_mem_operand" "am")))]
  ""
  "DAN %0,%2")

(define_insn "negsi2"
  [(set (match_operand:SI 0 "reg_or_mem_operand" "=a,m")
	(neg:SI (match_operand:SI 1 "acc_or_mem_operand" "am,a")))]
  ""
  "@
   LNA %0,%1
   SNA %0,%1")

(define_insn "negdi2"
  [(set (match_operand:DI 0 "accumulator_operand" "=a")
	(neg:DI (match_operand:DI 1 "acc_or_mem_operand" "am")))]
  ""
  "DLN %0,%1")

(define_insn "abssi2"
  [(set (match_operand:SI 0 "acc_or_mem_operand" "=a,m")
	(abs:SI (match_operand:SI 1 "acc_or_mem_operand" "am,a")))]
  ""
  "@
   LMA %0,%1
   SMA %0,%1")

(define_insn "absdi2"
  [(set (match_operand:DI 0 "accumulator_operand" "=a")
	(abs:DI (match_operand:DI 1 "acc_or_mem_operand" "am")))]
  ""
  "DLM %0,%1")

(define_insn "LNMA"
  [(set (match_operand:SI 0 "accumulator_operand" "=a")
	(neg:SI (abs:SI (match_operand:SI 1 "acc_or_mem_operand" "am"))))]
  ""
  "LNMA %0,%1")

(define_insn "mulsi3"
  [(set (match_operand:SI 0 "accumulator_operand" "=a")
	(mult:SI (match_operand:SI 1 "accumulator_operand" "%0")
		 (match_operand:SI 2 "acc_or_mem_operand" "am")))]
  ""
  "MSI %0,%2")

(define_insn "mulsidi3"
  [(set (match_operand:DI 0 "accumulator_operand" "=a")
	(mult:DI (sign_extend:DI
		  (match_operand:SI 1 "accumulator_operand" "%0"))
		 (sign_extend:DI
		  (match_operand:SI 2 "acc_or_mem_operand" "am"))))]
  ""
  "MI %0,%2")

(define_insn "DI"
  [(set (subreg:SI (match_operand:DI 0 "accumulator_operand" "=a") 0)
        (truncate:SI
	 (div:DI
	  (match_operand:DI 1 "accumulator_operand" "0")
	  (sign_extend:DI (match_operand:SI 2 "acc_or_mem_operand" "am")))))
   (set (subreg:SI (match_dup 0) 1)
        (truncate:SI (mod:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))]
  ""
  "DI %0,%2")


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Shifting and Rotating

;    73 00    SSC   Single Shift Circular
;    73 01    DSC   Double Shift Circular
;    73 02    SSL   Single Shift Logical
;    73 03    DSL   Double Shift Logical
;    73 04    SSA   Single Shift Algebraic
;    73 05    DSA   Double Shift Algebraic

; TARGET_1108up
;    73 07    DLSC  Double Load Shift and Count
;    73 10    LSSC  Left Single Shift Circular
;    73 11    LDSC  Left Double Shift Circular
;    73 12    LSSL  Left Single Shift Logical
;    73 13    LDSL  Left Double Shift Logical


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Logical Operations

(define_insn "notsi2"
  [(set (match_operand:SI 0 "reg_or_mem_operand" "=a,m")
	(not:SI (match_operand:SI 1 "acc_or_mem_operand" "am,a")))]
  ""
  "@
   LNA %0,%1
   SNA %0,%1")

(define_insn "notdi2"
  [(set (match_operand:DI 0 "accumulator_operand" "=a")
	(not:DI (match_operand:DI 1 "acc_or_mem_operand" "am")))]
  ""
  "DLN %0,%1")

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "accumulator_operand" "=a")
        (ior:SI (match_operand:SI 1 "accumulator_operand" "%0")
                (match_operand:SI 2 "acc_or_mem_operand" "am")))]
  ""
  "OR %0,%2")

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "accumulator_operand" "=a")
        (xor:SI (match_operand:SI 1 "accumulator_operand" "%0")
                (match_operand:SI 2 "acc_or_mem_operand" "am")))]
  ""
  "XOR %0,%2")

(define_insn "andsi3"
  [(set (match_operand:SI 0 "accumulator_operand" "=a")
        (and:SI (match_operand:SI 1 "accumulator_operand" "%0")
                (match_operand:SI 2 "acc_or_mem_operand" "am")))]
  ""
  "AND %0,%2")


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Floating-point Arithmetic

(define_insn "addsf3"
  [(set (match_operand:SF 0 "accumulator_operand" "=a")
	(plus:SF (match_operand:SF 1 "accumulator_operand" "%0")
		 (match_operand:SF 2 "acc_or_mem_operand" "am")))]
  ""
  "FA %0,%2")

(define_insn "adddf3"
  [(set (match_operand:DF 0 "accumulator_operand" "=a")
	(plus:DF (match_operand:DF 1 "accumulator_operand" "%0")
		 (match_operand:DF 2 "acc_or_mem_operand" "am")))]
  "TARGET_1108up"
  "DFA %0,%2")

(define_insn "subsf3"
  [(set (match_operand:SF 0 "accumulator_operand" "=a")
	(minus:SF (match_operand:SF 1 "accumulator_operand" "0")
		 (match_operand:SF 2 "acc_or_mem_operand" "am")))]
  ""
  "FAN %0,%2")

(define_insn "subdf3"
  [(set (match_operand:DF 0 "accumulator_operand" "=a")
	(minus:DF (match_operand:DF 1 "accumulator_operand" "0")
		 (match_operand:DF 2 "acc_or_mem_operand" "am")))]
  "TARGET_1108up"
  "DFAN %0,%2")

(define_insn "negsf2"
  [(set (match_operand:SF 0 "reg_or_mem_operand" "=a,m")
	(neg:SF (match_operand:SF 1 "acc_or_mem_operand" "am,a")))]
  ""
  "@
   LNA %0,%1
   SNA %0,%1")

(define_insn "negdf2"
  [(set (match_operand:DF 0 "accumulator_operand" "=a")
	(neg:DF (match_operand:DF 1 "acc_or_mem_operand" "am")))]
  ""
  "DLN %0,%1")

(define_insn "abssf2"
  [(set (match_operand:SF 0 "acc_or_mem_operand" "=a,m")
	(abs:SF (match_operand:SF 1 "acc_or_mem_operand" "am,a")))]
  ""
  "@
   LMA %0,%1
   SMA %0,%1")

(define_insn "absdf2"
  [(set (match_operand:DF 0 "accumulator_operand" "=a")
	(abs:DF (match_operand:DF 1 "acc_or_mem_operand" "am")))]
  ""
  "DLM %0,%1")

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "accumulator_operand" "=a")
	(mult:SF (match_operand:SF 1 "accumulator_operand" "%0")
		 (match_operand:SF 2 "acc_or_mem_operand" "am")))]
  ""
  "FM %0,%2")

(define_insn "muldf3"
  [(set (match_operand:DF 0 "accumulator_operand" "=a")
	(mult:DF (match_operand:DF 1 "accumulator_operand" "%0")
		 (match_operand:DF 2 "acc_or_mem_operand" "am")))]
  "TARGET_1108up"
  "DFM %0,%2")

(define_insn "divsf3"
  [(set (match_operand:SF 0 "accumulator_operand" "=a")
	(div:SF (match_operand:SF 1 "accumulator_operand" "0")
		(match_operand:SF 2 "acc_or_mem_operand" "am")))]
  ""
  "FD %0,%2")

(define_insn "divdf3"
  [(set (match_operand:DF 0 "accumulator_operand" "=a")
	(div:DF (match_operand:DF 1 "accumulator_operand" "0")
		(match_operand:DF 2 "acc_or_mem_operand" "am")))]
  "TARGET_1108up"
  "DFD %0,%2")
