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   ----- Transcript of session follows -----
Connected to CERBERUS.RICE.EDU:
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To: arpanet-bboards@mc.lcs.mit.edu
Subject: Applied formal methods for correct VLSI design.
Date: Tue, 31 Jan 89 17:19:55 EST
From: Mario Barbacci <mrb@sei.cmu.edu>
Resent-Date: 16 Feb 1989 00:27:13 EST
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==============================================================================
=                                                                            =
=                      C A L L   F O R   P A P E R S                         =
=                                                                            =
=               IFIP WG 10.2-10.5 International Workshop on:                 =
=                                                                            =
=              APPLIED FORMAL METHODS FOR CORRECT VLSI DESIGN.               =
=                                                                            =
=			13-16 November 1989.                                 =
=                                                                            =
=      imec Interuniversity Micro-Electronics Center Leuven Belgium          =
=                                                                            =
==============================================================================

Objectives
------------------------------------------------------------------------------
   This workshop is organized within the scope of IFIP WG 10.2 System Descrip-
tion and Design Tools in cooperation with  IFIP WG 10.5 Very Large Scale Inte-
gration.  It is the fifth  in a series organized by  IFIP WG 10.2  on  related 
areas of correct  hardware design  and verification. Previous conferences have
been  held in  Darmstadt (1984),  Edinburgh (1985),  Grenoble (1986),  Glasgow 
(1988).
   Functional  and  behavioral verification  of the correctness, is the bottle-
neck  of current VLSI design systems.  For economical reasons, designs  of VLSI 
circuits must be completely validated before manufacturing.  Current VLSI vali-
dation is  mainly done  through extensive simulation.  The emerging alternative
is  based on  formal design  and verification  methods, that guarantee correct-
ness.
   The  aim of this  workshop is to  bring together all researchers,  both from
academia and industry,  interested in formal  hardware design  methods that are
applicable for correct VLSI design. In order to achieve this, tutorials, exten-
ded  in-depth  overviews and  demonstrations of  CAD-tools making use of formal
methods will be organized  as well as regular presentations on current research
work.
   The  organization of practical demonstrations  as well as presentations will 
allow for more detailed informal contacts and discussions.

Regular presentations
------------------------------------------------------------------------------
   Papers describing  original work  in all aspects of  formal hardware design
methods are invited. Topics include, but are not limited to:

   . formal hardware verification methods
   . guided synthesis methods
   . high level specification
   . hardware description languages
   . use of theorem provers for verification
   . Boolean provers and tautology checking
   . MOS timing verification algorithms
   . switch level verification methods
   . RTL level verification
   . use of functional languages
   . correctness preserving transformations
   . formal proof of correctness
   . design for verifyability
   . practical experiences

   Prospective authors are invited to submit 3 copies of a paper, not exeeding
20 double spaced typewritten pages, to the Workshop Organizer by 1 July 1989.
   The proceedings will be published.

Demonstrations
------------------------------------------------------------------------------
   Proposals are invited for 30' presentations and accompanying demonstrations 
of CAD programs and prototype tools that illustrate recent research results or
original realizations in the area of formal hardware design methods.  The pro-
posal can either be a short  description of the demonstration or can be in the 
form of a regular presentation as described above. Proposals should be sent to
the Workshop Organizer before 1 July 1989.
   Workstations  will  be  made available on the conference site for demonsta-
tions.

Authors' schedule
------------------------------------------------------------------------------
   .  1 July      1989 : Deadline for submission of papers
   . 15 September 1989 : Notification of acceptance
   . 15 October   1989 : Camera-ready paper

Tutorials and in-depth Overviews
------------------------------------------------------------------------------
   During  the  workshop,  tutorials,  as  well  as more in-depth overviews on 
applied methods for formal hardware verification and design will be organized.

Benchmarking
------------------------------------------------------------------------------
   A set of benchmarks  for formal verification between  RTL specification and 
hardware implementation will be made available to interested participants. In-
terested participants  are invited to relate the practical benchmarks to their 
own work.  These will form the focus  point for special sessions with compari-
sons on methods used.

Participation
------------------------------------------------------------------------------
   The intention of this workshop  is to familiarize the participants with the
current state of the art,  and  new  directions of  research in applied formal 
methods for hardware design. Therefore, subscriptions for participation should
be made in time. Preregistrations by 1 October 1989.

Program Commitee
------------------------------------------------------------------------------
                Prof. F. Anceau (BULL FR)
                Prof. D. Borrione (IMAG Grenoble FR)
		Prof. R. Bryant (Carnegy Mellon University USA)
                Dr. L. Claesen (IMEC Leuven B)
                Dr. H. Eveking (Technische Hochschule Darmstadt FRG)
                Prof. M. Gordon (University of Cambridge UK)
                Prof. G.J. Milne (University of Strathclyde UK)
                Prof. P. Prinetto (Politecnico di Torino IT)
                Dr. P.A. Subrahmanyam (AT&T Holmdell USA)
             
------------------------------------------------------------------------------
Workshop Organizer:                       WG 10.5 representative:
   Luc Claesen                                Erik Schutz
   IMEC vzw                                   MIETEC nv
   Kapeldreef 75,                             Westerring 15
   B-3030 Leuven Belgium                      B-9700 Oudenaerde Belgium
   tel: +32-16-281203                         tel: +32-55-332211
   fax: +32-16-229400
   email: claesen@imec.uucp

------------------------------------------------------------------------------

Name:     _____________________________________________________________
Address:  _____________________________________________________________
          _____________________________________________________________

O  Please put me on the mailing list           Please reply to:
O  I am interested in participating                  Luc Claesen
O  I am interested in presenting a paper             IMEC vzw
O  I am interested in benchmarking                   Kapeldreef 75
O  I want to give a tutorial                         B-3030 Leuven
O  I am prepared to give a demonstration             Belgium

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Date: Thu, 16 Feb 89 07:58:58 PST
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   ----- Transcript of session follows -----
%MAIL-E-NOSUCHUSR, no such user FERRIBY at node TOCV18
550 <ferriby%toccl1.gm@HAC2ARPA.HAC.COM>... User unknown

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To: arpanet-bboards@mc.lcs.mit.edu
Subject: Applied formal methods for correct VLSI design.
Date: Tue, 31 Jan 89 17:19:55 EST
From: Mario Barbacci <mrb@SEI.CMU.EDU>
Resent-Date: 16 Feb 1989 00:27:13 EST
Resent-From: Arpanet-BBoards-Bugs@MC.LCS.MIT.EDU
Resent-To: Arpanet-BBoards-Distribution@MC.LCS.MIT.EDU
Resent-Comment: Send postings to ARPANET-BBOARDS@MC.LCS.MIT.EDU
Resent-Comment: Subscriptions to ARPANET-BBOARDS-REQUEST@MC.LCS.MIT.EDU
Resent-Comment: BITNETers use LISTSERVer ARPABBS on UBVM or TSCVM


==============================================================================
=                                                                            =
=                      C A L L   F O R   P A P E R S                         =
=                                                                            =
=               IFIP WG 10.2-10.5 International Workshop on:                 =
=                                                                            =
=              APPLIED FORMAL METHODS FOR CORRECT VLSI DESIGN.               =
=                                                                            =
=			13-16 November 1989.                                 =
=                                                                            =
=      imec Interuniversity Micro-Electronics Center Leuven Belgium          =
=                                                                            =
==============================================================================

Objectives
------------------------------------------------------------------------------
   This workshop is organized within the scope of IFIP WG 10.2 System Descrip-
tion and Design Tools in cooperation with  IFIP WG 10.5 Very Large Scale Inte-
gration.  It is the fifth  in a series organized by  IFIP WG 10.2  on  related 
areas of correct  hardware design  and verification. Previous conferences have
been  held in  Darmstadt (1984),  Edinburgh (1985),  Grenoble (1986),  Glasgow 
(1988).
   Functional  and  behavioral verification  of the correctness, is the bottle-
neck  of current VLSI design systems.  For economical reasons, designs  of VLSI 
circuits must be completely validated before manufacturing.  Current VLSI vali-
dation is  mainly done  through extensive simulation.  The emerging alternative
is  based on  formal design  and verification  methods, that guarantee correct-
ness.
   The  aim of this  workshop is to  bring together all researchers,  both from
academia and industry,  interested in formal  hardware design  methods that are
applicable for correct VLSI design. In order to achieve this, tutorials, exten-
ded  in-depth  overviews and  demonstrations of  CAD-tools making use of formal
methods will be organized  as well as regular presentations on current research
work.
   The  organization of practical demonstrations  as well as presentations will 
allow for more detailed informal contacts and discussions.

Regular presentations
------------------------------------------------------------------------------
   Papers describing  original work  in all aspects of  formal hardware design
methods are invited. Topics include, but are not limited to:

   . formal hardware verification methods
   . guided synthesis methods
   . high level specification
   . hardware description languages
   . use of theorem provers for verification
   . Boolean provers and tautology checking
   . MOS timing verification algorithms
   . switch level verification methods
   . RTL level verification
   . use of functional languages
   . correctness preserving transformations
   . formal proof of correctness
   . design for verifyability
   . practical experiences

   Prospective authors are invited to submit 3 copies of a paper, not exeeding
20 double spaced typewritten pages, to the Workshop Organizer by 1 July 1989.
   The proceedings will be published.

Demonstrations
------------------------------------------------------------------------------
   Proposals are invited for 30' presentations and accompanying demonstrations 
of CAD programs and prototype tools that illustrate recent research results or
original realizations in the area of formal hardware design methods.  The pro-
posal can either be a short  description of the demonstration or can be in the 
form of a regular presentation as described above. Proposals should be sent to
the Workshop Organizer before 1 July 1989.
   Workstations  will  be  made available on the conference site for demonsta-
tions.

Authors' schedule
------------------------------------------------------------------------------
   .  1 July      1989 : Deadline for submission of papers
   . 15 September 1989 : Notification of acceptance
   . 15 October   1989 : Camera-ready paper

Tutorials and in-depth Overviews
------------------------------------------------------------------------------
   During  the  workshop,  tutorials,  as  well  as more in-depth overviews on 
applied methods for formal hardware verification and design will be organized.

Benchmarking
------------------------------------------------------------------------------
   A set of benchmarks  for formal verification between  RTL specification and 
hardware implementation will be made available to interested participants. In-
terested participants  are invited to relate the practical benchmarks to their 
own work.  These will form the focus  point for special sessions with compari-
sons on methods used.

Participation
------------------------------------------------------------------------------
   The intention of this workshop  is to familiarize the participants with the
current state of the art,  and  new  directions of  research in applied formal 
methods for hardware design. Therefore, subscriptions for participation should
be made in time. Preregistrations by 1 October 1989.

Program Commitee
------------------------------------------------------------------------------
                Prof. F. Anceau (BULL FR)
                Prof. D. Borrione (IMAG Grenoble FR)
		Prof. R. Bryant (Carnegy Mellon University USA)
                Dr. L. Claesen (IMEC Leuven B)
                Dr. H. Eveking (Technische Hochschule Darmstadt FRG)
                Prof. M. Gordon (University of Cambridge UK)
                Prof. G.J. Milne (University of Strathclyde UK)
                Prof. P. Prinetto (Politecnico di Torino IT)
                Dr. P.A. Subrahmanyam (AT&T Holmdell USA)
             
------------------------------------------------------------------------------
Workshop Organizer:                       WG 10.5 representative:
   Luc Claesen                                Erik Schutz
   IMEC vzw                                   MIETEC nv
   Kapeldreef 75,                             Westerring 15
   B-3030 Leuven Belgium                      B-9700 Oudenaerde Belgium
   tel: +32-16-281203                         tel: +32-55-332211
   fax: +32-16-229400
   email: claesen@imec.uucp

------------------------------------------------------------------------------

Name:     _____________________________________________________________
Address:  _____________________________________________________________
          _____________________________________________________________

O  Please put me on the mailing list           Please reply to:
O  I am interested in participating                  Luc Claesen
O  I am interested in presenting a paper             IMEC vzw
O  I am interested in benchmarking                   Kapeldreef 75
O  I want to give a tutorial                         B-3030 Leuven
O  I am prepared to give a demonstration             Belgium

1,,
Date: Mon, 27 Feb 89 18:22:23 EST
From: Communications Satellite <COMSAT@MC.LCS.MIT.EDU>
Subject: Msg of Thursday, 23 February 1989 16:46-EST
To: ARPANET-BBOARDS-BUGS@MC.LCS.MIT.EDU
Message-ID: <1951.890227@MC.LCS.MIT.EDU>

*** EOOH ***
Date: Mon, 27 Feb 89 18:22:23 EST
From: Communications Satellite <COMSAT@MC.LCS.MIT.EDU>
To:   ARPANET-BBOARDS-BUGS@MC.LCS.MIT.EDU
Re:   Msg of Thursday, 23 February 1989 16:46-EST

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Date: Wed, 22 Feb 89 10:11 N
From: "Rob A. Vingerhoeds / Ghent State University" <ROB%BGERUG51.BITNET@MITVMA.MIT.EDU>
Subject: Neural Networks Seminar, 25 april 1989, Ghent, Belgium
To: occam@prg.oxford.ac.UK, transputer@prg.oxford.ac.UK,
 arpanet-bboards@mc.lcs.MIT.EDU, conferences@hplabs.hp.COM
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                 BIRA SEMINAR ON NEURAL NETWORKS

   When and how will Neural Networks become applicable for Industry?

                          25 APRIL 1989

               International Congress Centre Ghent

                             BELGIUM


BIRA (Belgian Institute for Control Engineering and Automation) is
organising a seminar on the state of the art in Neural Networks. The
central theme will be "When and how will neural networks become applicable
for industry". To be able to give a good and reliable verdict to this
theme, some of the most important and leading scientists in this fasci-
nating area have been invited to present a lecture at the seminar and take
part in a panel discussion.

The following schedule is foreseen:

 8.30 -  9.00    Registration
 9.00 -  9.15    Opening on behalf of BIRA
                 Prof. L. Boullart, Ghent State University
 9.15 - 10.00    Learning Algorithms and applications in A.I.
                 Prof. Fogelman Soulie, Universite de Paris V
10.00 - 10.30    coffee
10.30 - 11.30    The Neural Network Framework
                 Prof. B. Kosko, University of Southern California
11.30 - 12.00    Presentation of ANZA+ products, hardware and software
                 Patrick Dumont, Digilog, France
12.00 - 14.00    lunch / exhibition
14.00 - 15.00    Integration of knowledge-based system and neural network
                 techniques for robotic control
                 Dr. David Handelman, Princeton, USA
15.00 - 16.00    Application in Image Processing and Pattern Recognition
                 (Neocognitron)
                 Dr. S. Miyake, ATR, Japan
16.00 - 16.30    tea
16.30 - 17.15    panel discussion over the central theme
17.15 - 17.30    closing and conclusions

The seminar will be held in the same period as the famous Flanders
Technology International (F.T.I.) exhibition is held. This exhibition is
for both representatives from industry and for other interested people very
interesting and going to both the seminar and the exhibition is double
interesting. It is possible to obtain a ticket for F.T.I. at a reduced
price, when attending the seminar. Please indicate, whether you would like
to get a ticket, when sending in a letter or an e-mail message.

Prices:

members of BIRA :       12.500 BEF
others          :       15.000 BEF
universities    :        7.500 BEF

If you intent to attent our seminar, you can either send a letter to the
BIRA coordinator (adress follows) or an e-mail message to one of us. We will
fill you in on the details as soon as possible.


Rob Vingerhoeds               Leo Vercauteren
<ROB@BGERUG51.BITNET>         <LEO@BGERUG51.BITNET>


BIRA Coordinator: L. Pauwels
                  BIRA-secretariaat
                  Het Ingenieurshuis
                  Desguinlei 214
                  2018 Antwerpen
                  Belgium
telefax:          +32-3-216-06-89
                  (attn. BIRA L. Pauwels)
